Content-addressable (associative) memory devices

ABSTRACT

A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel word-organized associative memory having an array of associative memory cells arranged to be capable of bit-parallel search and write operations. A bit-serial associative memory having an array of memory cells arranged to be capable of bit-serial search and write operations, but not word bit-parallel search and write operations, is also included. The bit-serial memory is operatively connected to the bit-parallel memory and arranged to operate as an extension of the same. The method comprises searching the bit-parallel word-organized associative memory and/or the bit-serial associative memory coupled to the bit-parallel memory for data matching search data, and marking the memory cells having stored data matching the search data.

FIELD OF THE INVENTION

[0001] The present invention concerns improvements relating toAssociative or Content-Addressable Memory (CAM) devices and moreparticularly, though not exclusively, to an improved CAM data memoryorganisation for use with data-parallel associative processors such asSingle Instruction Multiple Data (SIMD) associative data-parallelprocessors.

BACKGROUND OF THE PRESENT INVENTION

[0002] A particular sub-class of SIMD data-parallel processors is knownas associative processors. Such processors utilise a class of memoryknown as associative or content-addressable memory (CAM). Such memories,as the name implies, do not operate by addressing the memory location inthe conventional sense, but rather they compare the stored contents of apre-defined field (or set of bits) of all memory words with a global bitpattern (comprising one or more bits). Those memory words which matchthe applied pattern during the operation (which is variously known assearching, matching or tagging) are marked in some way (tagged) in orderthat they might subsequently participate in a later operation whichwill, in some manner, modify the stored contents of the memory.

[0003] The internal organisation of such memories are generallyclassified into

[0004] 1. word organised (i.e. memories whereby a bit-parallel patternmay be used as the basis of the search) and the bit-parallel comparisonis carried out in a single indivisible operation, or

[0005] 2. bit-serial (i.e. only a single bit may be used as the basis ofthe search).

[0006] In the latter class of memories, bit-parallel searches may beemulated by repeated application of bit-serial searches.

[0007] Some applications of content-addressable memories follow thesearch phase with a match resolution phase, whereby a single matchingmemory location is uniquely located (generally the first from the top)and then updated—generally in the form of a conventional memory writecycle.

[0008] Applications of content-addressable memory for parallelprocessing make use of a programmable multi-write opportunity, wherebythe many tagged memory words may all (or a selected subset) be updatedsimultaneously.

[0009] The major attributes of such a memory are:

[0010] natural parallelism, whereby multiple memory words may be taggedin parallel; natural parallelism, whereby multiple memory words may besubsequently updated or modified in parallel.

[0011] Such memories are universally implemented as either bit-serial orword-organised. Some examples of CAM bit-serial and bit-parallel datamemories are provided in the following patents: U.S. Pat. No. 4,799,192which is directed to a three transistor content addressable memory; U.S.Pat. No. 4,833,643 which concerns associative memory cells; U.S. Pat.No. 4,991,136 which is directed to a semiconductor associative memorydevice with memory refresh during match and read operations; and U.S.Pat. No. 4,965,767 associative memory having simplified memory cellcircuitry. Early instances of the invention have been manufactured foruse with the Aspex ASP (Associative String Processor) data parallelprocessor. The ASP is a SIMD data processor that in typicalconfigurations operates on 1024 to 65536 data items in parallel. Some ofthe invention's detail is specific to this data processor. The majorattributes of the latest version of the ASP are 1152 processing elementson a single device 12.0 mm×12.0 mm in size and 100 MHz clock speed.Future versions of this processor will incorporate up to 8192 processingelements.

[0012] Conventional word-organised associative (content-addressable)memory can take many forms but a simple and common exemplary solution isnow described with reference to FIG. 1. FIG. 1 shows a simple memorycell 10 which comprises a static RAM cell 12 together with a form ofEXNOR network 14, which implements in use an equivalence comparisonbetween the stored state in the RAM cell 12 and a broadcast bit value tobe compared with.

[0013] The memory write cycle comprises the application of the data andNOT(data) to the bit lines 16 and a strobe on the word line 18. Thememory search cycle comprises a precharge of the match line 20, with thebit lines 16 held low (to prevent a discharge path to ground), followedby the release of the precharge and the application of the search data(and NOT(data)) onto the bit lines 16. If the stored and applied dataare different, then the match line 20 will discharge.

[0014] Such an organisation may be configured into a word-organisedmemory by simply creating a word-array on common match and word lines18, 20. Any mismatch on any bit(s) will result in the common match line20 discharging.

[0015] Implicit masking of any bit-column during a search cycle can becarried out by holding both the bit lines 16 low. However, there is asignificant disadvantage in that this style of memory cell 10 isrestricted to unconditional write of all bits of the stored data word,because of the common word line 18 (i.e. masked writes are notpossible). If individual fields or bits of the memory word are to beupdated, then multi-write (the capability to update more than one wordat a time) is impossible. A large number of variants exist for memorycells to fulfil this role but they all suffer from the same problem.

[0016] The present invention aims to overcome this problem and provide afar more flexible solution to the existing CAMs 10 described above.

SUMMARY OF THE INVENTION

[0017] According to one aspect of the present invention there isprovided a compound associative memory for use with a data-parallelcomputer, the memory comprising: a bit-parallel word-organisedassociative memory comprising an array of associative memory cellsarranged to be capable of bit-parallel search and write operations; abit-serial associative memory comprising an array of memory cellsarranged to be capable of bit-serial search and write operations, butnot word bit-parallel search and write operations; wherein thebit-serial memory is operatively connected to the bit-parallel memoryand arranged to operated as an extension of the same.

[0018] The present invention is able to overcome the problems of theprior art as it is possible to write to specific bits of a data word inthe compound associative memory whilst still retaining the ability tocarry out data-parallel data searches.

[0019] The new associative memory architecture of the present invention,in one embodiment, utilises a conventional three-transistorpseudo-static RAM circuit to provide a very dense memory to augment a 10transistor pseudo-static CAM cell of a type already used in theinventors' ASP technology.

[0020] As mentioned above, the compound memory essentially comprises twobanks, one of fully associative (word-organised) content-addressablememory, and the other of bit-serial associative memory. This lattermemory bank is referred to as extended memory. In an exemplaryembodiment, the two banks share common match lines and common writelines which enables them to function in a unified manner.

[0021] This compound memory as a whole is restricted to operations of abit-serial nature (i.e. it is incapable of sustaining word-organised(bit-parallel) search or write operation). However, the bank of fullyassociative (word-organised) content-addressable memory retains thiscapability. The restriction to bit serial memory enables theconstruction of the extended memory to be simplified there by reducingcost, complexity and power consumption.

[0022] Preferably the design of the extended memory organises thethree-transistor RAMs so that conventional direction of the memory wordsis aligned with the memory columns of the word-organised ten-transistorpseudo-static CAM array.

[0023] It is to be appreciated that the term column as used herein isintended to mean the direction of columns in the word-organised CAMmemory.

[0024] The operation of an embodiment of the present invention is nowdescribed in overview. When presented with a column address for a searchoperation, the column of memory cells in the extended memory isaccessed. Preferably a sense amplifier at the end of each word row isemployed to speed up the detection of the read event, even though theread cycle produces fully restored logic values. The output of the senseamplifier feeds a split EXNOR comparator similar to that employed ineach of the fully associative (word-organised) content-addressablememory cells, allowing the memory bank to be coupled directly onto thematch lines of the fully associative (word-organised)content-addressable memory. This ensures that the match line behaviourof the compound memory is uniform.

[0025] In keeping with the behaviour of the fully associative(word-organised) content-addressable memory, a write-back to theselected column of the extended memory is preferably in the form of amulti-write, wherein a number (between none and all) of memory bits willmodified, in those word rows denoted as active as a result of thesearch.

[0026] Those bits in the selected column, which need to be modified,receive a strobe on the word row write line and the global write data iswritten. Those bits where a strobe on the word row write line does nottake place are recirculated and written back (refreshed).

[0027] Aspects of the present invention which are highly advantageousare specified below. The present invention provides combinedword-organised and bit-serial memories in a single compound memory,allowing several advantageous functions to be carried out, namely:

[0028] emulation of bit-serial associative searching and writingbehaviour for the entire memory, irrespective of whether the data iscontained in the word-organised or extended memory blocks.

[0029] associative processing capability whereby the outcome of thesearch cycle is used to define an active set of word rows to participatein a subsequent multi-write, where the multi-write may occur in eitherthe word-organised CAM or the extended memory (or both),

[0030] clear or write of selected active bits is implemented by readingthe entire column and recirculating the stored data from the non-activebits whilst writing modifying and writing back the new global data valueinto all the active bits

[0031] compatibility with the two-bits-at-a-time serial search mode ofthe second bank of fully associative (word-organised)content-addressable memory,

[0032] adoption of a conventional three-transistor pseudo-static memorycell as the building block of the bit-serial associative memory,resulting in

[0033] substantial area and power savings compared to the fullyassociative (word-organised) content-addressable memory

[0034] The compound memory is restricted to operations of a bit-serialnature (i.e. it is incapable of sustaining word-organised (bit-parallel)search or write operation). However, the bank of fully associative(word-organised) content-addressable memory retains this capability.

[0035] The use of a bit-serial extended memory utilising onlythree-transistor RAM as associative memory provides significantadvantages such as:

[0036] Size. The improved density of the extended memory usingthree-transistor DRAM allows up to three times the density of theword-organised CAM memory.

[0037] Speed. The lower bit line capacitance allows the memory tooperate at a higher speed than the conventional word-organised CAM towhich it is an adjunct. Although this is not readily exploited in adevice which implements the dual-memory solution, and dedicated devicewith only extended memory style CAM would offer higher speed.

[0038] Power. The lower bit line capacitance allows the memory tooperate at a lower power per operation. This is highly advantageous asin VLSI (Very Large Scale Integration) of the memories there are verylarge numbers of operations that are carried out.

[0039] These benefits open a number of new application areas. Theapplication of this network to VASP processors advantageously allows thearchitecture to continue to exploit the non-deterministic nature of theassociative processor, whilst implementing effective numeric processingof a higher performance per unit area than conventional DSP (DigitalSignal Processing) solutions.

[0040] The present invention also extends to a method of storing data ina compound associative memory, the method comprising: searching abit-parallel word-organised associative memory capable of bit-parallelsearch and write operations and/or a bit-serial associative memorycoupled to the bit-parallel memory, which is capable of bit-serialsearch and write operations, but not word bit-parallel search and writeoperations, for data matching search data; marking the memory cellshaving stored data matching the search data; and storing data in atleast one of the marked memory cells, wherein the storing step comprisesreading data stored in the bit-serial memory and using the read data tocontrol selection of selective bits of the data organised as words inthe bit-parallel memory.

[0041] According to another aspect of the present invention there isprovided a word organised content-addressable memory (CAM) array for usewith an associative data-parallel processor, the CAM array comprising: aplurality of CAM cells arranged as a series' of data words, each cellrepresenting a bit of a word, the CAM cells being interconnected in ainterleaved manner to define odd and even alternating cells within adata word and being arranged to provide concurrent access to two-bits ata time of data stored in each data word in the CAM array.

[0042] This aspect of the present invention provides an improvement overconventional CAM arrays in that by use of the interleaving arrangementit is possible to increase the speed of operation, and enhance thenumeric capabilities of the memory.

[0043] Preferably, each cell comprises a plurality of match signalinglines for indicating the matching of the stored bit within the cell andpredetermined data. This provides a preferred way of exploiting the CAMarray to enable the data to be read from different adjacent interleavedpairs of cells concurrently. In fact, in an embodiment of this aspect ofthe present invention, a CAM array comprised of a plurality of splitmatch line pseudo-static or static-CAM memory cells is used togetherwith interleaved connection of cells in even-odd bit pairs to providefour-bits-at-a-time access to data stored in each word in the CAM array.

[0044] In the exemplary embodiment of this aspect of the presentinvention, exploiting the split match line CAM cell (which givestwo-bits-at-a-time numeric access of bits from the memory word) inconjunction with interleaving the bit cells to producefour-bits-at-a-time access into the CAM word, only requires the additionof two extra metal word lines which has no or negligible area impact onthe memory array size. This advantageously improves speed by reducingthe capacitance on a given bit line, and improves the throughput byeffectively doubling the numeric processing by increasing the access tofour bits-at-a-time.

[0045] The present invention also extends to a method of retrievingmultiple bits of data from a data word in a word organisedcontent-addressable memory (CAM) array, the method comprising: carryingout a bit-serial search of a plurality of different columns of memorycells of the CAM array, the search involving masking the data lines toall but the specified plurality of columns of cells and placingcomplementary search data on the different data lines of the pluralityof non-masked columns; matching the complementary search data with datastored in the memory cells; and generating a non-matching signal if thestored data does not match the search data on any of the cells beingtested; wherein by virtue of an interleaved interconnection of the CAMcells to matching lines and the use of complementary search data, thenon-matching signal is a signal representative of the CAM cell's storedvalue.

[0046] Preferred embodiments of the present invention will now bedescribed by way of example with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0047]FIG. 1 is a circuit diagram showing the arrangement of a prior-artSRAM-based CAM cell;

[0048]FIG. 2 is a schematic block diagram showing an associative memorysystem showing main and extended memory banks according to a firstembodiment of the present invention;

[0049]FIG. 3 is a circuit diagram showing an ASP word-organisedten-transistor CAM cell used within the associative memory system shownin FIG. 2;

[0050]FIG. 4 is a circuit diagram showing an alternative non-explicitmask CAM cell to that shown in FIG. 3;

[0051]FIG. 5 is a circuit diagram showing a three-transistor extendedmemory cell of the extended memory of FIG. 2;

[0052]FIG. 6 is a schematic block diagram showing in detail anextended-memory word row adaptor of FIG. 2; and

[0053]FIG. 7 is a circuit diagram showing a match-line sense amplifierused in the associative memory system shown in FIG. 2;

[0054]FIG. 8 is a schematic block diagram showing an associative memorycomprising interleaved memory bits according to a further embodiment ofthe present invention; and

[0055]FIG. 9 is a showing an extended-memory organisation fortwo-bits-at-a-time operation of the further embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] A chip content-addressable compound memory 50 according to anembodiment of the present invention is now described with reference toFIG. 2. The memory structure 50 essentially comprises: a word-organisedcontent-addressable memory array (CAM) 52, a memory row interface 54 forinterfacing to a SIMD processor for implementing an associative dataread/write; a bit-serial extended memory block 56 for supplementing theoperation of the CAM array 52 and an extended memory row adaptor 58 forinterfacing the extended memory 56 to the CAM array 52. In the presentembodiment the CAM array 52 comprises 128 word rows with each word being64 bits wide. The extended memory 56 comprises words that are columnaligned and that are 128 bits wide to match the number of rows in theCAM array 52.

[0057] In addition to these main blocks, the CAM array 52 is providedwith a bit-line interface controller 60 for selecting bits within datawords of the CAM array 52 for reading and writing to. Similarly, theextended memory block 56 has a corresponding column decoder and bit-linecontroller 62. The extended memory row adaptor 58 also has a global datainterface 64 for receiving data on a serial search and writing data tothe extended memory block 56.

[0058] The extended memory 56 is linked to the CAM array 52 via theextended memory row adaptor 58 and common signal lines, namely aplurality of word row write lines 100, a plurality of match-on-zerolines 101 and a plurality of match-on-one lines 102. In this embodimentthere are 128 match-on-zero lines 101, 128 match-on-one lines 102 and 64word row write lines 100.

[0059] The operation of the compound memory 50 is typical broken downinto four phases, namely: pre-search; search; activate; and write (orread). Taking each of these in turn, the pre-search phase supports theprecharging of the word-aligned match lines 101, 102 and the pre-fetchof the search data. The operation of the compound memory 50 can beeither bit-serial or bit-parallel. However, the extended memory block 56can only be used in bit-serial mode. During the pre-search cycle, thememory bit-column is decoded, by the column decoder and bit-linecontroller 62, and the search data is registered into the global datainterface 64 of the extended memory row adaptor 58. At the same time abit-parallel search pattern (not shown) is loaded into the CAM bit-lineinterface controller 60. In the case of a bit-serial operation, only onebit of this pattern contains valid search data.

[0060] During the search cycle, if the extended memory block 56 isenabled then the selected column is read out into the extended memoryrow adaptor 58 (which comprises essentially logic gates) and thenpropagated to the main memory row interface 54 via the CAM match lines101, 102. If the extended memory is not active then the search takesplace in the main CAM array 52. In this case, the extended memory block56 is not utilised and therefore can undertake a normal column refreshcontrolled by external refresh logic. Although not pertinent to theexplanation of the present invention, the results of the search cycle(in the form of match/mismatch indications of the cell match lines101,102) are propagated via the memory row interface 54 and stored intoappropriate registers in the adjacent word logic. Matching word rows aresaid to be tagged.

[0061] During the activate cycle, a programmable mapping between taggedand active word rows is effected. The interval is also used to implementa column refresh in the extended memory 56 under control of externalrefresh logic (not shown) and a block refresh in the pseudo-static CAM(described in detail below).

[0062] During the write cycle, the active word rows participate in amulti-write. The word row write enables 100 of active word rows becometrue. If the write operation is designated to take place in the CAMarray 52, then the bit-parallel write pattern presented to the bit-linecontrol logic is written into the designated words. The ability of thebit-line controller 60 to mask bits from the write operation enables theCAM array 52 to emulate bit-serial operations (where only one bit iswritten) or to undertake a flexible set of bit-parallel write options.

[0063] If the CAM array 52 is selected, then a direct read of the storeddata can also take place. Under these circumstances it is required thatonly one word row of the memory should be enabled. Such an option caneasily be implemented. A number of conventional CAM solutions provide amatch resolver to select the first matching word row, which is then usedto generate an row address for subsequent read or write. A variant onthis scheme may be used to make (say) only the first word row active fora read cycle.

[0064] If the write operation is designated to take place in theextended memory block 56 (bit-serial only), then the CAM bit-lines areusually all masked by the bit-line controller 60. During an extendedmemory write operation, the column to be written is first read out intothe extended memory word row adaptor 58. Those bits in the column whichare to write data, receive a strobe on the word lines 100 only in activeword rows and the bit-serial write data is distributed and written toeach bit. Those bits where a strobe event on the write line does nottake place have their pre-read data recirculated and writtenback—identical to the behaviour during a refresh. Such behaviouremulates the other feature of an associative processor, namely themulti-write of selected word rows.

[0065] It is to be appreciated that word-oriented read operations of theextended memory block 56 cannot take place.

[0066] Referring now to FIG. 3, an example of an ASP word-organisedmemory cell 200 that is used in the CAM array 52 of the presentembodiment is now described. This class of memory cell 200 can be seen(with minor variations) in the VASP-256 and VASP-1024 data-parallelprocessors by the present applicant. There are several features of theimplementation of note. Firstly, the memory cells 200 are of an all NMOSconstruction, which leads to a higher density of cells. Secondly, thistype of memory cell 200 enables explicit masking of the write operationto allow selected bits of the memory word(s) to be updated—therebyallowing the emulation of bit-serial operation, combined withmulti-write capability, which is an essential feature in the operationof the CAM as part of an associative processor. Thirdly, the memorycells utilise split match lines. This feature allows the creation ofseparate match-on-zero (M₀) and match-on-one (M₁) indicators, whichimprove the functionality of the memory cell as will be explained later.

[0067] The operation of this circuit during a write cycle is nowdescribed. The write cycle requires the data to be applied to net 203and NOT(data) to net 204. A valid write enable must be stable andapplied to net 205 before the word line 206 of the cell column isstrobed, and it must be retained until after the strobe is negated. Onlycells 200 in bit-columns whose write enable net 205 is driven to V_(CC)will be modified with a word whose word line 206 is strobed.

[0068] The maximum voltage which can be stored on either net 201 or 202is limited to one threshold below the supply, given that signals on nets203, 204, 205 and 206 are driven to the fixed positive supply potentialV_(CC).

[0069] Refresh of this pseudo-static arrangement can be affected bysetting the signal voltages on the nets 203, 204, and 205 to beequivalent to the supply, namely equal to V_(CC) and then strobing theword line 206 as per a write cycle. The state of nets 203 and 204 mustbe sustained at or near V_(CC) by restoring drivers of sufficiently highgain so as to be sensibly unaffected by the current drain though nets201 or 202, whichever is storing data 0. Because the memory cell 200 iseffectively self restoring under the conditions where the voltages onthe nets 203, 204, 205 and 206 are equivalent to the supply voltagenamely V_(CC), then an opportunity exists to undertake a simultaneousrefresh of more than one word row. In parallel processingconfigurations, where CAMs comprising several thousand words may befound, the requirement to refresh each word separately may lead tosignificant numbers of lost machine cycles in order that the externalrefresh logic can introduce refresh cycles with sufficient frequency soas to retain the stored state of the entire memory. By refreshing anumber of words simultaneously in this manner (say 16), the percentageof lost cycles is reduced. However, such a multi-row refresh can only besustained if the state of nets 203 and 204 can be held at or near V_(CC)by restoring drivers of sufficiently high gain so as to be sensiblyunaffected by the current drain imposed by multiple memory cells enabledfor refresh simultaneously. Moreover the dissipated power during therefresh cycle will be substantially higher.

[0070] The operation of the circuit during a search cycle requires amatch-on-one line 207 and match-on-zero line 208 to be precharged to thefixed positive supply potential V_(CC), whilst ensuring that the bitlines 203 and 204 are held at ground potential.

[0071] The application of TRUE data (where net 203 has a voltageequivalent to V_(CC), and net 204 has a voltage equivalent to GND(ground)) to a memory cell storing a data value of zero (i.e. net 201has a voltage equivalent to GND, and net 202 has a voltage equivalent toV_(CC)-V_(T)) will result in the discharge of the match-on-one line 207,indicating a mismatch for search data TRUE.

[0072] The application of FALSE data (where net 203 has a voltageequivalent to GND, and net 204 has a voltage equivalent to V_(CC)) to amemory cell storing a data value of one (i.e. net 201 has a voltageequivalent to V_(CC)-V_(T), and net 202 has a voltage equivalent to GND)will result in the discharge of match-on-zero line 208, indicating amismatch for search data FALSE.

[0073] All other valid search conditions (including a masked searchwhere net 203 and net 204 each have a voltage equivalent to GND) willresult in the match lines remaining precharged—indicating a matchingsearch.

[0074] An example of this kind of bit-parallel content addressablememory is found in the VASP-1024 data-parallel processor comprising a64-bit by 1024 word memory array.

[0075] A variant of the CAM described above in the first embodiment isnow described as a second embodiment of the present invention withreference to FIG. 4. This embodiment is very similar to the firstembodiment and so only the differences will be described hereinafter toavoid unnecessary repetition. The major difference is that the CAMmemory cell 300 and the CAM array 52 are different as is the way inwhich the CAM array 52 is configured to effect a associative bit-writeoperation.

[0076] The variant 300 of the CAM cell 200 shown in FIG. 3 removes therequirements for an explicit column write enable 205 for each column ofthe CAM array 52, although at the expense of a higher power requirementduring masked write operations.

[0077] The operation of this memory cell circuit 300 during a writecycle requires the data to be applied to net 303 and NOT(data) to net304. The word line 306 is strobed, and it must be retained until afterthe strobe is negated. Those cells 300 where no write is required havelines 303 and 304 set to the positive supply potential V_(CC) to effecta so called ‘non-explicit’ masking of the cell. This works because thecell is a pseudo-static cell which does not change state when there isno charge difference between its data line inputs. These cells 300undertake an automatic and user transparent self-refresh operation.

[0078] However, given that the number of cells 200 undertaking this formof transparent self refresh is non-deterministic and may vary from noneto all, the ability to control the substantially higher power generatedduring this operation is limited, unlike the normal refresh (see below).Consequently, this places a sensible upper limit on the use of thismemory variant, despite the area saving due to the removal of twotransistors and a column write enable 205.

[0079] The maximum voltage which can be stored on either net 301 or 302is limited to one threshold below the supply, given that signals on nets303, 304 and word line 306 are driven to the fixed positive supplypotential V_(CC).

[0080] Refresh of this pseudo-static arrangement can be effected bysetting the signal voltages on the nets 303 and 304 to be equivalent tothe positive supply, namely equal to V_(CC) and then strobing the wordline 306 as per a write cycle. The state of nets 303 and 304 must besustained at or near V_(CC) by restoring drivers of sufficiently highgain so as to be sensibly unaffected by the current drain though nets301 or 302, whichever is storing data 0. Because the cell 300 iseffectively self-restoring under the conditions the voltages on the nets303, 304, and 306 are equivalent to the supply voltage namely V_(CC),then an opportunity exists to undertake a simultaneous refresh of morethan one word row. In a parallel processing configurations, where CAMscomprising several thousand words may be found, the requirement torefresh each word separately may lead to significant numbers of lostmachine cycles in order that the external refresh logic can introducerefresh cycles with sufficient frequency so as to retain the storedstate of the entire memory. By refreshing a number of wordssimultaneously in this manner (say 16), the percentage of lost cycles isreduced. However, such multi-row refresh can only be sustained if thestate of nets 303 and 304 can be held at or near V_(CC) by restoringdrivers of sufficiently high gain so as to be sensibly unaffected by thecurrent drain imposed by multiple memory cells 300 enabled for refreshsimultaneously. Moreover the dissipated power during the refresh cyclewill be substantially higher.

[0081] An example of this kind of bit-parallel content addressablememory is found in the VASP-256 data parallel processor, which comprisesa 64-bit by 256 word memory array.

[0082]FIG. 5 shows a well-known three-transistor memory cell circuit 400that is used for the cells of the extended memory 56 in the compoundassociative memory 50 of the present embodiment. However, unlike theconventional orientation of this cell 400, the read and write enablelines 405, 406 are aligned to the memory column, whilst the read andwrite data lines 403, 404 are aligned with the memory row.

[0083] The operation of this cell 400 during a write cycle comprises theapplication of write data in signal 403, accompanied by a strobe cycleon the write enable line 406. The hold requirements of signal 403 withrespect to signal 406 must be adhered to. The write data and writeenable lines 403, 406 are driven to the fixed positive supply potentialV_(CC) during a write (or refresh) cycle. The data stored on node 402,the gate of device 407, is limited to one threshold below the supply,which is sufficient to exceed the ‘on’ threshold of device 407 for avalid read event.

[0084] During a read cycle, the read data line 404 is precharged. Oncethe precharge is released, the read enable line 405 is asserted. Alogical ‘one’ stored at node 402 (V_(CC)-V_(T)) will enable a dischargepath for the read data line 404. A logical ‘zero’ stored at node 402will disable the discharge path and leave the read data line 404precharged. Effectively this signal represents NOT(data).

[0085] Variations on this cell, wherein the read transistors 407, 408,connected between the READ DATA line and ground, are reversed in orderare well known and well documented.

[0086] Referring now to FIG. 6, the Memory Row Interface Adaptor 58,which interfaces the extended memory 56 to the CAM array 52, is shown.This adaptor 58 serves the diverse purposes of:

[0087] 1. carrying out a qualified precharge of the read net,

[0088] 2. carrying out sense-amplification of the read net data,

[0089] 3. latching of the read data for timing consistency duringrefresh/rewrite cycles and

[0090] 4. implementing EXNOR behaviour which ensures signalcompatibility with the match-on-zero and match-on-one match lines 207,208 of the CAM array 52.

[0091] The overall timing of the extended memory array 56 is qualifiedby two timing phases, φ₁ and φ₂ which are used to regulate the access tothe read and write data lines 403, 404. The general timing is:

[0092] 1. φ₁ qualifies a read event

[0093] 2. φ₂ qualifies a write/refresh event and also the read lineprecharge.

[0094] During the first phase φ₁, a memory cell 503 of the extendedmemory 56 is enabled to read its data onto a read data line 501. Thisinformation is sensed by a transparent latch 505, which is also enabledby the first phase be, and whose input stage is appropriately ratioed toprovide a switching point around 65% of the fixed supply voltage. Underall circumstances the read line 501 will have been precharged.

[0095] During a search cycle, the resulting READ_DATA is used as theinput to the EXNOR networks 506, which ensure signal compatibility withthe match-on-zero and match-on-one match lines 207, 208 of the CAM array52. The READ_DATA is gated with a signal SE1 (Search Enable 1, a signalcreated from the logical AND of search enable and the complement of theglobal bit-serial search data digit) to generate the MATCH-ON-ONEoutput. This output is directly coupled onto the equivalent match signal207 in the corresponding CAM array word row. Similarly the READ_DATA isgated with a signal SE0 (search enable 0, a signal created from thelogical AND of search enable and the bit-serial search data digit) togenerate the MATCH-ON-ZERO output. This output is also directly coupledonto the equivalent match signal 208 in the corresponding CAM array wordrow.

[0096] At the same time an opportunistic refresh of the extended memorycolumn is enabled, wherein the READ_DATA is recirculated onto the writedata line 502 to be re-written into the memory cell 503 whose WRITEENABLE (see FIG. 3) strobe is derived from the column address qualifiedwith the second phase φ₂.

[0097] During a write event, the cycle commences with a column readduring the first phase φ₁. The memory cell 503 is enabled to read itsdata onto the read data line 501. This information is sensed by thetransparent latch 505, which is also enabled by the first phase φ₁, andwhose input stage is appropriately ratioed to provide a switching pointaround 65% of the fixed supply voltage.

[0098] Under all circumstances the read line 501 will have beenprecharged by the second phase 42. The role of the transparent latch 505is to retain the data read during the first phase φ₁ throughout thesecond phase φ₂ (the writeback) when the read line 501 has becomeinvalid due to the precharge.

[0099] During the second phase φ₂, a word row which has been denoted tobe active (see above) has its word enable (WE) line asserted. In theabsence of a refresh (i.e. REFRESH=0), the global WRITE_DATA will bedriven onto the write data line 502 to be written into the memory cell503 whose WRITE ENABLE (see FIG. 3) strobe 205 is derived from thecolumn address qualified with the second phase φ₂. At the same time, aword row which has been denoted to be inactive (see above) has its wordenable (WE) line de-asserted. In this case the READ_DATA is recirculatedonto the write data line 502 to be re-written into the memory cell 503as before.

[0100] The present embodiment of the invention allows the conventional3-transistor DRAM memory cell 503 to emulate the behaviour of theword-organised CAM 52 (when operating in serial mode) in all respects,including:

[0101] 1. split match line (match-on-zero and match-on-one) behaviourduring search;

[0102] 2. masked search; and

[0103] 3. multi-write of data only in active word-rows.

[0104] Operation of the extended memory 56 is limited to single bitaccess. Operation of the overall memory system (i.e. the compound memory50 comprising extended memory 56 and CAM array 52) in two-bits-at-a-timeserial mode (i.e. arithmetic) can only support access to one bit fromthe extended memory 56 and one bit from the CAM array 52.

[0105] Referring to FIG. 7, a match line sense amplifier 600 is shownwhich a component of the memory row interface 54. This is used toenhance the evaluation of the implementation. As can be seen, each matchline 207, 208 is routed via the simple sense amplifier network 600,which comprises a ratioed inverter set to between 65% and 75% of thesupply voltage (V_(CC)) depending upon the local match line load. Thispermits the equalisation of the mismatch discharge period acrossmultiple match lines 207, 208.

[0106] The output of the sense amplifier 600 is used to gate thepull-down of an independent precharged match output net for circuitspecific reasons. The precharge device for the primary match line ismirrored by a discharge device which is utilised to ensure that thematch lines 207, 208 do not retain charge outside of valid searchevents, which can be the basis of induced cross-talk paths.

[0107] In both the first and second embodiments, the role of split matchlines 207, 208, 307, 308 in numeric processing in the associativeprocessor is now discussed.

[0108] By offering split match lines (match-on-one—M₁, andmatch-on-zero—M₀) in the above described embodiments, the data-parallelassociative processor (not shown) is actually able to efficientlyemulate two-bits-at-a-time access of column data from the CAM 52.

[0109] This is performed by ensuring that a bit-serial search isperformed on two columns, with all other columns masked. One column mustbe searched with data 0 and the other with data 1. Generally thenominated bit columns represent corresponding bits from two separate (orcontiguous) fields of the memory word which are allocated to differentoperands (e.g. operand A and operand B) as shown below: operand Aoperand B word row n operand A operand B word row n + 1 operand Aoperand B word row n + 2 operand A operand B word row n + 3

[0110] For that column searched with data 1 (where net 203=V_(CC), net204=GND), then:

[0111] 1. Only the match-on-one line 207 can possibly discharge;

[0112] 2. If data stored is ‘1’, then the search yields a match and theprecharged match-on-one line 207 remains precharged at V_(CC) (‘1’); and

[0113] 3. If data stored is ‘0’, then the search yields a mismatch andthe precharged match-on-one line 207 is discharged to GND (‘0’).

[0114] Thus the stored memory column is effectively read out onto thematch-on-one line 207.

[0115] For that column searched with data 0 (where net 203=GND, net204=V_(CC)), then:

[0116] 1. Only the match-on-zero line 208 can possibly discharge;

[0117] 2. If data stored is ‘0’, then the search yields a match and theprecharged match-on-zero line 208 remains precharged at V_(CC) (‘1’);and

[0118] 3. If data stored is ‘1’, then the search yields a mismatch andthe precharged match-on-zero line 208 is discharged to GND (‘0’).

[0119] Thus the complement of the stored memory column is effectivelyread out onto the match-on-zero line 208.

[0120] Referring now to FIG. 8. A third embodiment of the presentinvention is described. Again for the avoidance of unnecessaryrepetition, only the differences between the first and third embodimentsof the present invention are discussed hereinafter.

[0121] The major difference between the above-mentioned embodiments isthat the third embodiment comprises interleaved memory bits in theword-organised CAM array 52, 700. The purpose of such an arrangement isto improve (reduce) power dissipation, and to enhanced arithmeticcapability of the compound memory 50 (or an associative processor usingthe memory). More specifically, the CAM words 702 comprising a pluralityof CAM cells 704 are organised on an odd/even interleaved basis, withsplit match lines 706, 707, 708, 709 and split word lines 710, 712.

[0122] Each even memory cell 704, 714 in the CAM word 702 has its splitmatch cell outputs (match-on-one—M₁, and match-on-zero—M₀), onlyattached to the even match lines (707 and 708). Even bits canparticipate in two-bits-at-a-time access of column data from the evenbits of the CAM 700.

[0123] This is performed by ensuring that a bit-serial search isperformed on any two even columns 716, with all other columns (exceptfor the two columns 718 nominated as odd—see below) masked. One column716 is searched with data 0 and the other 716 with data 1. Generally thenominated bit columns 716 are corresponding bits from fields of thememory word 702 allocated to different operands.

[0124] For that column 716 searched with data 1 (where the data lines720=V_(CC), 722=GND), then:

[0125] 1. Only match-on-one (even) 708 can possibly discharge.

[0126] 2. If data stored is ‘1’, then the search yields a match and theprecharged match-on-one (even) line 708 remains precharged at V_(CC)(‘1’).

[0127] 3. If data stored is ‘0’, then the search yields a mismatch andthe precharged match-on-one (even) line 708 is discharged to GND (‘0’).

[0128] Thus the stored memory column 716 is effectively read out ontothe match-on-one (even) line 708.

[0129] For that column searched with data 0 (where the data lines720=GND, 722=V_(CC)), then:

[0130] 1. Only match-on-zero (even) 707 can possibly discharge.

[0131] 2. If data stored is ‘0’, then the search yields a match and theprecharged match-on-zero (even) line 707 remains precharged at V_(CC)(‘1’).

[0132] 3. If data stored is ‘1’, then the search yields a mismatch andthe precharged match-on-zero (even) line 707 is discharged to GND (‘0’).

[0133] Thus the complement of the stored memory column 716 iseffectively read out onto the match-on-zero (even) line 707.

[0134] Each odd memory cell 704,724 in the CAM word 702 has its splitmatch cell outputs (match-on-one—M₁, and match-on-zero—M₀), onlyattached to the odd match lines 705, 706. Odd bits can participate intwo-bits-at-a-time access of column data from the odd bits of the CAM700.

[0135] This is performed by ensuring that a bit-serial search isperformed on any two odd columns, with all other columns 718 (except forthe two columns 716 nominated as even—see above) being masked. Onecolumn 718 must be searched with data 0 and the other 718 with data 1.Generally the nominated bit columns are corresponding bits from fieldsof the memory word 702 allocated to different operands.

[0136] For that column 718 searched with data 1 (where the data lines726=V_(CC), and 728=GND), then:

[0137] 1. Only match-on-one (odd) 706 can possibly discharge.

[0138] 2. If data stored is ‘1’, then the search yields a match and theprecharged match-on-one (odd) line 706 remains precharged at V_(CC)(‘1’).

[0139] 3. If data stored is ‘0’, then the search yields a mismatch andthe precharged match-on-one (odd) line 706 is discharged to GND (‘0’).

[0140] Thus the stored memory column 718 is effectively read out ontothe match-on-one (odd) line 706.

[0141] For that column searched with data 0 (where the data lines726=GND, and 728=V_(CC)), then

[0142] 1. Only match-on-zero (odd) 705 can possibly discharge.

[0143] 2. If data stored is ‘0’, then the search yields a match and theprecharged match-on-zero (odd) line 705 remains precharged at V_(CC)(‘1’).

[0144] 3. If data stored is ‘1’, then the search yields a mismatch andthe precharged match-on-zero (odd) line 705 is discharged to GND (‘0’).

[0145] Thus the complement of the stored memory column 718 iseffectively read out onto the match-on-zero (even) line 705.

[0146] The present embodiment allows the CAM word 702 to effectivelyoperate in bit-serial mode, whilst allowing simultaneous access to up tofour bits 704 at a time from a given memory word 702. This enables fourbits at-a-time arithmetic and logical operations to be implemented. Theresulting design also has the benefits:

[0147] 1. no (or no significant) area penalty in the memory cell 704;and

[0148] 2. a modest power penalty, due only to the extra metalcapacitance associated with the additional pair of match lines. Howeverthe match line connections overall (i.e. the source-drain areas attachedto the match lines) which constitute the largest contribution ofcapacitance—and therefore power—remains constant. Moreover inconventional 1-bit-at-a-time or 2-bits-at-a-time operation, the searchmatch-line power dissipation is halved due to the reduced capacitance onany given match line.

[0149] The resulting four match lines can then be propagated to either:

[0150] 1. A two-bit adder/ALU (not shown), or

[0151] 2. A single adder/ALU (not shown) which is time multiplexed toproduce a two-bit result.

[0152] This embodiment is applicable whichever implementation isadopted. It is also to be appreciated that the interleavedword-organised CAM array 700 does not necessarily have to be implementedin a compound memory 50 as has been described above. It can be used asan improved but non-extended associative memory for a data-parallelprocessor.

[0153] Consistent with the requirements of two-bits-at-a-time orfour-bits-at-a-time operation of the word-organised CAM (when operatingin bit-serial mode), the extended memory cell can be enhanced to supportdual-port access as is now described with reference to FIG. 9. Whichshows a modified extended memory cell 800. Layout benchmarks show thatthis design is only some 12% larger than the single-port equivalent,whilst offering a 100% improvement in arithmetic processing throughput.

[0154] The extended memory block 56 comprises an array of even and oddmemory cells 800, which enable two bits at-a-time operation. Taking eachof these in turn:

[0155] The operation of each memory cell 800 wired as an even bit duringa write cycle comprises the application to that cell 800 of even-bitwrite data in signal 807, accompanied by a strobe cycle on the evenwrite enable line 810. The hold requirements of data on 807 with respectto 810 must be adhered to. The even write-data and even write enablelines 810, 807 are driven to the fixed positive supply potential V_(CC)during a write (or refresh) cycle. The data stored on node 815, the gateof device (FET) 814, will be limited to one threshold below the supply,which is sufficient to exceed the on threshold of device 814 for a valideven or odd read event.

[0156] During an even read cycle, the even read data line 805 isprecharged. Once the precharge is released, the even read enable isasserted on line 809. A logical ‘one’ stored on 815 (V_(CC)-V_(T)) willenable a discharge path via the device 802 for the even read data line805. A logical ‘zero’ stored on 815 will disable the discharge path viathe device 802 and leave the read data net 805 precharged. Effectivelythis signal represents NOT(data).

[0157] The operation of each memory cell 801 wired as an odd bit duringa write cycle comprises the application of odd-bit write data in signal808, accompanied by a strobe cycle on the odd write enable line 812. Thehold requirements of data on 808 with respect to 812 must be adhered to.The odd write data and odd write enable lines 808, 812 are driven to thefixed positive supply potential V_(CC) during a write (or refresh)cycle. The data stored on node 804, the gate of device 803, will belimited to one threshold below the supply, which is sufficient to exceedthe ‘on’ threshold of device 803 for a valid even or odd read event.

[0158] During an odd read cycle, the odd read data line 806 isprecharged. Once the precharge is released, the odd read enable isasserted on line 811. A logical ‘one’ stored on 804 (V_(CC)-V_(T)) willenable a discharge path via the device 802 for the odd read data line806. A logical ‘zero’ stored on 804 will disable the discharge path viathe device 802 and leave the read data net 806 precharged. Effectivelythis signal represents NOT(data).

[0159] The operation of these memory cells 800 and 801 is complementedwith a duplication of the memory row interface adaptor circuit shown inFIG. 6. This sustains the search, write and refresh behaviour of thetwo-bit (word-parallel, bit-serial) DRAM access, whilst coupling to thefour match lines 796, 707, 708, 709 available in the CAM 700 toimplement the overall compound memory search behaviour.

[0160] Search and write access of the extended memory is limited to twobits at-a-time. Operation of the overall memory system (i.e. thecompound memory comprising extended memory and CAM) in fourbits-at-a-time serial mode (i.e. arithmetic) can only support access totwo bits from extended memory and two bits from the CAM (or all fourbits from the CAM).

[0161] The compound memory 50 has been implemented in a VASP-1024 chipwith 64 bits of extended memory, together with one-bit-at-a-timeassociative access combined with two-bits-at-a-time CAM.

[0162] Having described particular preferred embodiments of the presentinvention, it is to be appreciated that the embodiments in question areexemplary only and that variations and modifications such as will occurto those possessed of the appropriate knowledge and skills may be madewithout departure from the spirit and scope of the invention as setforth in the appended claims.

1. A compound associative memory for use with a data-parallel computer,the memory comprising: a bit-parallel word organized associative memorycomprising an array of associative memory cells arranged to be capableof bit-parallel search and write operations; a bit-serial associativememory comprising an array of memory cells arranged to be capable ofbit-serial search and write operations, but not word bit-parallel searchand write operations; wherein the bit-serial memory is operativelyconnected to the bit-parallel memory and arranged to operated as anextension of the same.
 2. A compound associative memory according toclaim 1, wherein the organization of memory cells into words in thebit-serial memory is aligned transversely with the organization ofmemory cells into words in the bit-parallel memory.
 3. A compoundassociative memory according to claim 1, wherein at least one dimensionof the array of the bit-serial associative memory is equivalent to adimension of the array of the bit-parallel word organized memory.
 4. Acompound associative memory according to claim 1, further comprisingconfiguring means for reading data stored in the bit-serial memory andfor using the read data to control selection of selective bits of thedata organized as words in the bit-parallel memory.
 5. A compoundassociative memory according to claim 4, wherein the bit-parallel memorycomprises a plurality of write enable lines aligned transversely withthe organization of memory cells into words in the bit-parallel memoryand the configuring means is arranged to use words read from thebit-serial memory to select write enable lines in the bit-parallelmemory.
 6. A compound associative memory according to claims 1, whereinthe memory cells of the data-parallel memory comprise pseudo-static CAMcells and bit-parallel memory comprises a data bit controller forcontrolling the data supplied to the cells of the bit-parallel memoryvia a plurality of data bit lines, wherein the controller is arranged toselectively mask off cells representing bits of a word in thebit-parallel memory in a non-explicit manner.
 7. A compound associativememory according to claim 4, wherein the configuring means comprises arow adaptor and convertor for converting the control signals of thebit-parallel memory to control signals suitable for use with thebit-serial memory.
 8. A compound associative memory according to claim7, wherein the row adaptor and convertor comprises an amplifier at theend of each word row for amplify the read data from cells of thebit-serial memory.
 9. A compound associative memory according to claim7, wherein the row adaptor and convertor comprises an exclusive ORcomparator for generating matching signals compatible with matchingsignals of the bit-parallel memory.
 10. A compound associative memoryaccording to claims 7, further comprising a global interface coupled tothe row adaptor means for inputting data into the bit-serial memory viathe row adaptor means.
 11. A compound associative memory according toclaim 1, wherein each cell of the bit-serial memory, comprises alow-power three transistor pseudo-static RAM circuit.
 12. A compoundassociative memory according to claim 11, wherein the RAM circuitcomprises read and write enable control lines aligned to a columnorientation of the memory cell and read and write data lines aligned toa row orientation of the memory cell.
 13. A compound associative memoryaccording to claim 1, wherein each cell of the bit-parallel memory iscoupled to a plurality of match signaling lines, each line indicating amismatching result of a data bit or data word search process within thebit-parallel memory.
 14. A compound associative memory according toclaim 13, wherein the plurality of match signaling lines are coupled tothe bit-serial memory to indicate mismatching results of a data bitsearch within the bit-serial memory.
 15. A compound associative memoryaccording to claim 14, wherein the memory cells of the bit-serial memoryare arranged to operate in a similar manner to the bit-parallel memorysuch that a plurality of bits corresponding to the number of matchsignaling lines can be retrieved simultaneously from the bit-serialmemory in a single undivisable operation.
 16. A compound associativememory according to claim 11, wherein the RAM circuit for each cellcomprises a plurality of read enable control lines, a plurality of writeenable control lines, a plurality of read data lines and a plurality ofwrite data lines coupled to the circuit.
 17. A compound associativememory according to claim 1, wherein the bit- parallel memory isarranged to support a two-bits-at-a-time serial data search mode and thebit-serial memory is arranged to support a compatible two-bits-at-a-timeserial data search mode.
 18. A compound associative memory according toclaim 1, further comprising control means arranged to control use of thebit-serial and bit-parallel memories to carry out bit-serial associativesearching and writing procedures for both the bit-serial andbit-parallel memories.
 19. A compound associative memory according toclaim 18, wherein the control means is arranged to carry out a clear orwrite operation of selective active cells of the bit-serial memory byreading an entire column of the bit-serial memory, recirculating thestored data from non-active cells of the bit-serial memory andoverwriting the data in each of the active cells with a global bit data.20. A compound associative memory according to claim 1, furthercomprising associated processing means arranged to use the results of abit-serial search cycle to define an active set of word row locations toparticipate in a subsequent multiple write operation in the bit-parallelmemory and/or the bit-serial memory.
 21. A combination of a dataparallel processor and a compound associative memory according toclaim
 1. 22. A method of storing data in a compound associative memory,the method comprising: searching a bit-parallel word organizedassociative memory capable of bit-parallel search and write operationsand/or a bit-serial associative memory coupled to the bit-parallelmemory, which is capable of bit-serial search and write operations, butnot word bit-parallel search and write operations, for data matchingsearch data; marking the memory cells having stored data matching thesearch data; and storing data in at least one of the marked memorycells, wherein the storing step comprises reading data stored in thebit-serial memory and using the read data to control selection ofselective bits of the data organized as words in the bit-parallelmemory.
 23. A word organized content-addressable memory (CAM) array foruse with an associative data-parallel processor, the CAM arraycomprising: a plurality of CAM cells arranged as a series of data words,each cell representing a bit of a word, the CAM cells beinginterconnected in an interleaved manner to define odd and evenalternating cells within a data word and being arranged to provideconcurrent read access to multiple bits of data stored in the data word.24. A CAM array according to claim 23, wherein each cell comprises aplurality of match signaling lines for indicating the matching of thestored bit within the cell and predetermined data.
 25. A CAM arrayaccording to claim 24, wherein each cell is connected to a match on oneoutput line for signaling when the stored data bit within the cell isnot the same as a logical one, and a match on zero output line forsignaling when the stored data bit within the cell is not the same as alogical zero.
 26. A CAM array according to claims 23, wherein pairs ofadjacent alternate cells (even or odd) are arranged to be compared tocomplementary data signals to carry out non-conflicting data reads ofthe adjacent alternate cells.
 27. A CAM array according to claim 26,wherein adjacent alternate cells are arranged be read simultaneously.28. A CAM array according to claims 23, further comprising a pluralityof data lines to each cell of the array.
 29. A CAM array according toclaim 28, wherein each data cell is provided with complementary valuedata lines.
 30. A CAM array according to claims 23, wherein the CAMarray further comprises a plurality of word enable control lines forenabling a series of cells comprising a word within the array.
 31. A CAMarray according to claim 30, wherein each cell is arranged to receive asingle word enable control line and each word enable control line isarranged to connect to adjacent alternate memory cells.
 32. A CAM arrayaccording to claims 23, wherein each word of the memory is provided in arow and the memory further comprises means for masking off columns ofcells to enable specific bits of a data word to be read.
 33. A compoundassociative memory according to claims 1, wherein the bit-parallelmemory comprises a CAM array according to claims
 23. 34. A method ofretrieving multiple bits of data from a data word in a word organizedcontent-addressable memory (CAM) array, the method comprising: carryingout a bit-serial search of a plurality of different columns of memorycells of the CAM array, the search involving masking the data lines toall but the specified plurality of columns of cells and placingcomplementary search data on the different data lines of the pluralityof non-masked columns; matching the complementary search data with datastored in the memory cells; and generating a non-matching signal if thestored data does not match the search data on any of the cells beingtested; wherein by virtue of an interleaved interconnection of the CAMcells to matching lines and the use of complementary search data, thenon-matching signal is a signal representative of the CAM cell's storedvalue.